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fef8 Voltage to frequency converters (VFCs) fef8 are a preferred methodology of fef8 noise-tolerant analog to digital conversion. fef8 Synchronous VFCs (just like the fef8 Analog Gadgets AD652) through which fef8 an exterior, normally crystal-derived, clock fef8 gives timing for the conversion fef8 course of, have vital efficiency fef8 benefits (pace, linearity, precision impartial fef8 of passive elements) over the fef8 free-running kind through which conversion fef8 timing should finally depend on fef8 an RC time fixed.
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fef8 However a attribute limitation of fef8 all VFCs, each synchronous and fef8 asynchronous, is that they make fef8 comparatively gradual analog-to-digital converters (ADCs) fef8 as a result of the fef8 full-scale output frequency, and subsequently fef8 conversion pace for any given fef8 conversion decision, is proscribed by fef8 the analog switches used within fef8 the conversion course of through fef8 which pace and precision are fef8 inherently inversely associated. This design fef8 concept ( fef8 Determine 1 fef8 ) pushes most correct working fef8 frequency past 1 MHz by fef8 using high-speed H-CMOS logic units fef8 as extraordinarily quick analog switches.
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fef8 Determine 1 fef8 The excessive pace synchronous VFC.
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fef8 Right here’s the way it fef8 works:
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fef8 D-type flip-flop #1 (FF#1) within fef8 the HC74 types a suggestions fef8 loop with op-amp #2 within fef8 the 6482 appearing as a fef8 high-resolution comparator and with the fef8 excessive pace (~ns transition occasions) fef8 of the HC74 switches appearing fef8 to use 0/5V to Q1 fef8 based on the 0/1 state fef8 of the op-amp output when fef8 the FF is clocked. The fef8 obligation cycle (DC1) of the fef8 FF is thus time averaged fef8 by R1C3 and servoed by fef8 the suggestions loop to power fef8 V fef8 R1C3 fef8 = 5V * DC1 fef8 = Vin and DC1 = fef8 Vin / 5V. However a fef8 logic provide is usually a fef8 poor alternative for a conversion fef8 reference voltage, so if this fef8 had been all there was fef8 to the story, expectations for fef8 VFC accuracy would likewise be fef8 poor. We’d like a trick fef8 to compensate for the inevitable fef8 inaccuracy and noise within the fef8 +5V provide.
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fef8 The wanted compensation is offered fef8 by FF#2 implementing one other fef8 suggestions loop.
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fef8 FF#2 is related to kind fef8 a monostable (one-shot) triggered by fef8 Fclk, making use of 5V fef8 pulses to the R4C4 averaging fef8 community with pulse length (T fef8 p fef8 ) decided by R2, R3, fef8 C1 community and op-amp #1. fef8 The voltage is averaged by fef8 V fef8 R4C4 fef8 = Fclk * 5V fef8 * T fef8 p fef8 . Op-amp #1 compares this fef8 common to Vref and forces fef8 T fef8 p fef8 in order that T fef8 p fef8 = Vref / Fclk fef8 / 5V. As a result fef8 of each FFs occupy the fef8 identical chip, accuracy-affecting parameters like fef8 propagation delays, transition occasions, and fef8 voltage offsets will likely be fef8 very comparable and monitor nicely fef8 over temperature and provide voltage fef8 variations, making compensation very efficient.
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fef8 These T length pulses turn fef8 into the clock reference for fef8 FF#1, thus…
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fef8 DC1 = Fout * T fef8 p fef8 / Fclk = Fout fef8 * Vref / Fclk / fef8 5V = Vin / 5V
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fef8 …yielding (lastly) the hoped-for classical fef8 synchronous VFC conversion equation…
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fef8 Fout / Fclk = Vin fef8 / Vref
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fef8 The ensuing VFC has some fef8 helpful traits in addition to fef8 excessive pace (for a VFC). fef8 This features a good linearity, fef8 a tolerance of Vref within fef8 the vary of 1 to fef8 4 V, Fclk from 500 fef8 kHz to three MHz, operation fef8 from a single “5V+”, a fef8 3 to six V provide, fef8 a low energy consumption (~10 fef8 mW), very excessive enter impedances fef8 (e.g., lower than 1pA enter fef8 present on Vin and Vref), fef8 and no essential or high-precision fef8 passive elements.
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fef8 Lastly, all components wanted to fef8 construct it are generic, available, fef8 and fef8 low-cost! fef8 Whole components value is ~$10, fef8 whereas against this the same fef8 pace AD652, by itself, prices fef8 ~$40.
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fef8 Stephen Woodward fef8 ‘s relationship with fef8 EDN’s fef8 DI column goes again fef8 fairly a methods. In all, fef8 a complete of 64 submissions fef8 have been accepted since his fef8 first contribution was revealed in fef8 1974.
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fef8 Associated Content material
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